1. Field of the Invention
The present invention relates to a memory device, compatible with a double data rate, for inputting and outputting data in synchronization with the leading edge and the trailing edge of a clock. In particular, the present invention pertains to a memory device for performing an innovative write-interrupt-read operation and a data mask operation.
2. Related Arts
Synchronous DRAM (SDRAM) for inputting and outputting data in synchronization with a clock has been drawing attention as DRAM with high-speed processing. SDRAM receives a command composed of a number of control signals and an address signal in synchronization with the leading edge of a clock, and receives and outputs data in synchronization with the leading edge of the clock.
SDRAM has a burst mode wherein, while a word line is kept to be driven, the reading or writing of a plurality of data sets is sequentially performed in response to read commands or to write commands. Since a plurality of data sets can be read or written in the burst mode, for a single the word line driving, and a sense amplifier activation/reset, the access time for each bit can be reduced.
For the burst write, a data mask operation is provided which inhibits the writing of data at an arbitrary timing. For example, in the burst writing of four bits, a data mask signal is supplied in synchronization with the input of the third write data, so that the writing of the third write data is inhibited.
In addition, a write interrupt-read-operation is provided by which, during burst write, a read command is supplied to forcibly terminate the burst write operation and to interrupt the read operation. In order to perform the write-interrupt-read operation, a data mask signal must be supplied before a read command is issued according to the specifications for SDRAM.
FIG. 6 is a diagram illustrating a column circuit in a conventional SDR (Signal Data Rate) type SDRAM. A plurality of memory cells are provided in a memory array MCA, each memory cell including one transistor and one capacitor which are located at the intersections of a word line WL and paired bit lines BL and /BL. A sense amplifier S/A is connected to the bit lines BL and /BL, and is connected via a column gate CLG to paired data bus lines DB and /DB. The column gate CLG is rendered conductive or non-conductive in accordance with a column select signal CL, which is issued by a column decoder CDEC.
A data input/output terminal DQ is connected to a data output buffer 10 and a data input buffer 12. Read data DOUT is transferred from a sense buffer S/B, which is activated during the reading process, to the data output buffer 10. Write data DIN is transferred from the data input buffer 12 to a write buffer W/A, which is activated during the writing process. A read/write clock CLK-RW is generated in response to a read command or to a write command, and upon receiving this clock CLK-RW, a column decoder control circuit 18 generates a column decoder activation signal CD to render the column decoder CDEC in the active state for a specific period of time. During this period of time, the column decoder CDEC continues to render the column gate CLG in the conductive state in accordance with the column select signal CL. In addition, during this period of time, a short transistor ST for short-circuiting the paired data bus lines is maintained in the non-conductive state.
A read enable signal RE is generated in accordance with a read command, and upon receiving the read enable signal RE, a sense buffer control circuit 14 generates a read control signal REN for rendering the sense amplifier S/B in the active state for the above specific period of time. In addition, a write enable signal WE is generated in accordance with a write command, and upon receiving this write enable signal WE, a write amplifier control circuit 16 generates a write control signal WEN for rendering a write amplifier W/A in the active state during the above period of time.
FIG. 7 is a timing chart showing the write-interrupt-read operation performed by the SDR type memory device in FIG. 6. In the example in FIG. 7 the burst length is 4. A write command WRITE is supplied in synchronization with the leading edge of a clock at time t0, and write data D0 and D1 are received in synchronization with the leading edges of clocks at time t0 and t1, respectively, and are written. A data mask signal DQM is supplied in synchronization with the leading edge of a clock at time t2, and a read command READ is supplied in synchronization with the leading edge of a clock at time t3. The reading operation interrupts the write operation.
Write data D0 to D3 are input at a data input/output terminal DQ in synchronization with the leading edges of clocks following time t0. These data are fetched into the data input buffer 12, and are transmitted as input data DIN to the write amplifier W/A. In response to the write command WRITE, an internal reading/writing clock CLK-RW is generated, and in response to this clock CLK-RW, the column decoder control circuit 18 generates a column decoder activation signal CD. In response to the column decoder activation signal CD, the column decoder CDEC generates a column select signal CL, so that the write amplifier control circuit 16 generates a write control signal WEN. Upon receiving the write control signal WEN, the write amplifier W/A drives the paired data bus lines DB and /DB in accordance with the write data, and writes the data via the column gate CLG to the memory cell MC.
The read/write clock CLK-RW is internally generated in synchronization with the leading edge of the clock CLK. In the example in FIG. 7, the write data D0 and D1, which are input at time t0 and time t1, are respectively written via the data bus lines DB and /DB to the memory cell MC.
Before the read command is interrupted at time t3, the data mask signal DQM is input at time t2 . In response to the input of the data mask signal DQM, an internal mask signal MASK is generated. Upon receiving the internal mask signal MASK, the write amplifier control circuit 16 does not generate a write control signal WEN, even when the write enable WE signal indicates the device is in the write enable state, so as to deactivate the write amplifier W/A and inhibit the writing of data D2. Further, when at time t3 the read command READ is supplied, the write enable signal WE is reset to the write disable state, and the write amplifier control circuit 16, which does not generate a write control signal WEN, deactivates the write amplifier W/A and inhibits the writing of the data D3. At the same time, the sense buffer control circuit 14 generates a read control signal REN in response to the read state of the read enable signal RE, and permits the sense buffer S/B to amplify the read data Q0, which are output to the data bus lines DB and /DB. The read data Q0 are transmitted to the data output buffer 10 in synchronization with the leading edge of the next clock at time t4, and are output at the data input/output terminal DQ in synchronization with the following clock at time t5.
The write amplifier control circuit 16 can inhibit the writing of data D2 only by deactivating the write amplifier W/A in response to the data mask signal DQM at time t2. Therefore, in response to the read/write clock CLK-RW, the column decoder control circuit 18 outputs the column decoder activation signal CD to generate a column select signal CL. As a result, the column gate CLG is opened, the paired data bus lines DB and /DB are driven by the sense amplifier S/A, and the read data Q2 are output thereto. It should be noted that the read data Q2 are data stored in the memory cell in association with the driving of the word line WL, and are not externally output because the sense buffer S/B is deactivated.
As is described above, according to a conventional SDRAM, first the data mask signal DQM is supplied and then the read command READ is supplied in order to forcibly interrupt the reading operation during the burst write operation. Therefore, in a clock cycle before the read command is supplied, the paired data bus lines DB and /DB are not driven at a large write amplitude by the write amplifier W/A. The data bus lines DB and /DB can be satisfactorily reset during an adequate period of time xT (shown in FIG. 7) before the read data are output to the data bus lines DB and /DB in accordance with the next read command.
Conventional SDRAM is an SDR (Single Data Rate) type which only inputs and outputs data in synchronization with the leading edge of a clock. A DDR (Double Data Rate) type memory device has been proposed which enables higher speed processing. The DDR type memory device inputs and outputs data in synchronization with the leading edge and the trailing edge of a clock. Therefore, a memory controller transmits data to and receives data from the memory device at a double data rate.
However, how the write interrupt-read-operation should be performed for the DDR type memory device has not been proposed. In addition, since the DDR type memory device has a circuit structure which differs from that of the SDR type memory device, it is difficult for the write-interrupt-read operation of conventional SDRAM be applied unchanged for the DDR type memory device.